I have posted an L2 cache enabling bootloader at http://www.dialectronics.com/bootloader/ This bootloader incorporates code I have written to dynamically calculate the size of the L2 cache and make relatively educated guesses about the L2CR value. This bootloader is useful for Macs that have upgrade cards in them for which there is insufficient Open Firmware support for OF to properly enable the L2 cache before loading the bootloader. Previously when this condition was encountered the L2 value would have to be compiled into the kernel and the L2 enabled when the CPU attached. Changes in CPU required a change in the kernel, and I thought perhaps this could be improved upon, especially since upgrades can be very cost effective. I have tested this bootloader on a 7600 w/ 300MHz G3 (running the prototype OpenBSD on Old World Macs that Maciej Swiderski and I have been working on) and on my AGP G4. When the bootloader encounters an already enabled L2 cache it does not change the initialized settings but will run a memory sizing test on it. It would not be difficult to expand the code to do a full battery of tests on the cache to ensure proper functionality. For G3 settings I have used 1:2 clock divider, pipeline burst SRAM, 0.5nS output hold, write through, ZZ enabled For G4 settings I have used 1:2, pb SRAM, 0.5 ns OH, write back, no ZZ For G4+ settings I have used 1:2, late write SRAM, third output hold, write back, no ZZ These are relatively conservative and common values I have come across in documentation. If someone wants more aggressive clock timing in can be compiled into the kernel, but the current kernel code in cpu.c does not handle changing settings of enabled caches particularly well and with a G4 it will quite likely always cause a crash. As part of the memory test I do change settings on G4s and have successfully changed them. While the G3 can be turned off as part of the testing, the G4 does not like this at all and also requires a dssall before changes. This opcode does not exist in 3.5-current's as compiler and had to be added as a .long call. It may also be possible to add the code to the kernel as a system call for dynamic testing. The code for this cache enabling is at http://www.dialectronics.com/PowerPC/code/L2Config.c and I have copyrighted it temporarily until there is a final release, at which time it will include the final copyright. While there are code samples from DINK32 and Ryan Rempel is also working on this problem, the code I used to calculate the cache size is unique and does not resemble other sources. Once I have added additional support for 7410 and higher cpus I will finalize the code. I have made what I believe to be reasonable values for the RAM type and clock divider settings for these cpus, but I do not have access to them so I can not guarantee operation with them at this time. I also hope to do L3 enabling as necessary as soon as I have access to a CPU with one. The code is well documented and should be easily understood for those familiar with cache hardware. At the bottom of this email is the output of a boot using the boot24t.mac with a custom 3.5-current. It has additional information not present in stock 3.5-current but the code for it can be found at http://www.dialectronics.com/OldWorldMacs/code/cpu.c The file is a compilation of three separate sources and the copyright(s) reflects this. The copyright may be subject to further refinement. The above cpu.c uses a modified powerpc/cpu.h that contains the following additional macros FUNC_SPR(936, ummcr0) FUNC_SPR(940, ummcr1) FUNC_SPR(952, mmcr0) FUNC_SPR(953, pmc1) FUNC_SPR(954, pmc2) FUNC_SPR(956, mmcr1) FUNC_SPR(957, pmc3) FUNC_SPR(958, pmc4) These macros are for the use of the Performance Monitor Counters that the cpu.c code uses to dynamically determine the CPU speed. The version of cpu.c above does not initially use Open Firmware to return the MHz value. This is because in the case of upgrade cards with CPUs OF does not recognize, OF will return 195MHz as the value. I combined a couple sources to use the performance monitors for the calculation and as the pmc2 value for count CPU cycles has stayed consistent across several PowerPC generations now, I felt that using this would be dependable and remove dependency on OF. In the event that PMCs are not present on the CPU, the code will default to using OF. I also combined a source that had extensive listing of CPU names and that is in the above cpu.c as well. This may or may not be appropriate, but it was available so I used it. The bootloader could use additional testers. While there may not be many OpenBSD users with upgraded Macs that do not enable the L2 automatically, the bootloader has been tested against NetBSD 1.5.3 successfully as well, so anyone who knows a NetBSD user that would be interested in this should forward this to them. If you have an upgrade CPU in your Mac w/ either BSD, I would be interested in seeing dmesgs from them in order to verify the frequency the default settings are correct and what variations I may have to consider. The bootloader is xcoff and so will boot on all OF Macs. For those of you who may be wondering about the progress on Old World Macs, progress is coming along well. Maciej and I are coming to a point where we need more testers (we have ourselves and one additional person who is currently less available than previously). Please reply offline if you are interested, and I will return a descriptive list of requirements for testing within the next two weeks. Session capture is one requirement as outputs from test releases will be necessary for debugging. I will attempt to be responsive to inquiries about the above code, but I will be unavailable during much of next week. The timing is not great, but I wanted to get this out before upcoming events at my end. tim 0 > boot fd:1,\boot24t.mac bsd35.gz loading XCOFF tsize=C810 dsize=364 bsize=A40 entry=24000 SECTIONS: ..text 00024000 00024000 0000C810 000000E0 ..data 00031000 00031000 00000364 0000C8F0 ..bss 00031368 00031368 00000A40 00000000 loading .text, done.. loading .data, done.. clearing .bss, done.. >> OpenBSD/macppc Boot configuring L1/L2/L3 caches... l2cr value before: 0 L2 currently disabled, trying... turning on base settings... autosizing... memory claimed (0x200000 at 0x32000)... memory test setting: b95c0000... measured memory size: 80000... memory released... L2 enabled with final setting: a9180000 L2 cache value: a9180000 no active package/ Kernel file opened... Header read... Executing ELF file... Reading segment 0...5460812+242616 Zero out bss... BSS maxp... End of segment 0 pass... FREE phdr... ELF and Section Headers... Frobbing... Returned from elf_exec...=5946580 (0x5abcd4u) chaining... entering initppc... trap vectors... syncicache... pmap_bootstrap... BATs... ranslation... initmsgbug... boot args... devio extent... ofwconsinit... console on serialCopyright (c) 1982, 1986, 1989, 1991, 1993 The Regents of the University of California. All rights reserved. Copyright (c) 1995-2004 OpenBSD. All rights reserved. http://www.OpenBSD.org OpenBSD 3.5-current (OWRAMDISK) #28: Mon May 17 02:00:48 CEST 2004 root [at] thor.my.domain:/usr/src/sys/arch/macppc/compile/OWRAMDISK real mem = 167772160 (163840K) avail mem = 138596352 (135348K) using 1254 buffers containing 8388608 bytes of memory mainbus0 (root) cpu0 at mainbus0: Motorola PowerPC 740/750 (G3 - Arthur) Rev. 2.2: 301 MHz HID0: 8090c0a4 l2cr value: a9180000: 512KB backside cache Pipelined synchronous burst SRAM mpcpcibr0 at mainbus0 (remainder of dmesg removed due to extensive debugging code)